1. Field of the Invention
The present invention relates to a system having multiple data flow processors and particularly to such a system capable of changing data flow processors communicating with a host computer from one to another.
2. Description of the Related Art
The data flow processor responds to packets sequentially inputted thereinto to execute a program which has been stored in the data flow processor. FIG. 2 shows the functional arrangement of the data flow processor. As shown in FIG. 3, a packet 20 comprises a data part 21 containing data to be processed by the data flow processor and a tag part 24 including an instruction 22 for instructing the data flow processor to perform the process and a destination number 23 storing a number corresponding to each address in the program to be executed.
The processing flow when the packet 20 is inputted into the data flow processor will be described below.
As seen from FIG. 2, the data flow processor 10 comprises an input/output control unit 11, a program storage unit 12 in which a program to be executed by the data flow processor 10 has been stored, a queuing unit 13 in which a packet read therein is temporarily held until another packet functioning as a companion in operation is read in the queuing unit 13, and a processing unit 14 for executing the operation.
After having been inputted into the input/output control unit 11 of the data flow processor 10, the packet 20 is fed to the program storage unit 12 wherein the instruction 22 to be executed and the destination number 23 are obtained by the data flow processor 10. If the instruction 22 included in the packet 20 is one to be executed as one of a pair of packets, the first packet 20 is held in the queuing unit 13 until the other packet 20 functioning as a companion in operation is inputted into the queuing unit 13. When the other packet 20 is fetched by tile queuing unit 13, the paired packets 20 are fed to tile processing unit 14 wherein the operation is executed. If the instruction 22 in the first packet 20 is not one to be executed as one of a pair of packets, the first packet 20 passes through the queuing unit 13 without being held and then goes to the processing unit 14 wherein the instruction 22 therein is executed. The contents of the packet 20 are updated when tile instruction 22 thereof is executed in the processing unit 14. The updated packet 20 is then fed back to the input/output control unit 11 from which it will be outputted to the other data flow processor 10 or the like connected to the data flow processor in question or fed to the program storage unit 12 in which tile operation thereto is again to be executed, depending on the updated contents of that packet 20.
If the instruction 22 included in a packet 20 is one for loading a program, an external program can be stored in the program storage unit 12 of the data flow processor 10 when packets 20 each containing part of that program are sequentially inputted into the data flow processor 10.
When the packets 20 are sequentially inputted into the data flow processor 10, thus, the latter can execute or store a specific processing program.
FIG. 4 shows a system having multiple data flow processors constructed in accordance with the prior art, which comprises a host computer 31 for transmitting packets 20, a first data flow processor 32 connected to the host computer 31 and adapted to receive packets 20 from the host computer 31 for performing the process, and a second data flow processor 33 connected to the first data flow processor 32 and adapted to receive packets 20 from the first data flow processor 32 for performing the process. The first and second data flow processors 32 and 33 may be of the same structure as that of the data flow processor 10 shown in FIG. 2.
The system having multiple data flow processors will operate as follows:
When the host computer 31 transmits data including packets 20 to tile first data flow processor 32, the communication between the host computer 31 and the first data flow processor 32 is tested. On termination of such a test, packets 20 are sequentially fed from the host computer 31 to the first data flow processor 32 to test the first data flow processor 32 in operation.
The operation of the second data flow processor 33 will then be tested through the first data flow processor 32 which has been tested in operation. First of all, the host computer 31 sequentially outputs packets 20 to the first data flow processor 32. On receipt of these packets 20, the data flow processor 32 performs a given process. The input/output control unit 11 of the first data flow processor 32 then outputs the corresponding packets 20 to the second data flow processor 33, depending on the updated contents of the packets 20. The operation of the second data flow processor 33 will be tested by the packets 20 fed thereto from the first data flow processor 32.
In such a manner, the proper operation of the prior art system having multiple data flow processors will be confirmed by testing the operation of the second data flow processor 33.
However, the system having multiple data flow processors of the prior art can test the operation of the second data flow processor 33 only through the first data flow processor 32. In other words, the operation of the second data flow processor 33 cannot be tested in isolation. Thus, the communication between only the first and second data flow processors 32, 33 cannot be tested. If any failure is found on testing the operation of tile second data flow processor 33, one cannot specify whether such a failure is in the communication between the first and second data flow processors 32, 33 or in the second data flow processor 33 itself.
If there is any failure in the first data flow processor 32, the operational test in the second data flow processor 33 can be made only after the failure has been removed from the first data flow processor 32. Therefore, the system having multiple data flow processors of tile prior art requires a lot of time to test the entire operation thereof.